40th IEEE VLSI Test Symposium 2022
نویسندگان
چکیده
The articles in this issue are divided into two groups: 1) the first group comprises selected from 40th IEEE VLSI Test Symposium 2022 and 2) second consists of general interest articles.
منابع مشابه
High-Level Test Generation using Physically-Induced Faults - VLSI Test Symposium, 1995. Proceedings., 13th IEEE
A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring,full detection of lowlevel, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding ,functional tests are derived (induced) from the circuit under test; ofparticulur interest are SSL-induced functional faults or SIFs. We...
متن کاملTransformed Pseudo-Random Patterns for BIST - VLSI Test Symposium, 1995. Proceedings., 13th IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The trang5ormation is performed by a small amount of mapping logic that decodes sets of patterns that don't detect any new faults and maps them into patt...
متن کاملTesting Embedded Cores Using Partial Isolation Rings - VLSI Test Symposium, 1997., 15th IEEE
Intellectual property cores pose a signifcant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the userdefine...
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ژورنال
عنوان ژورنال: IEEE design & test
سال: 2023
ISSN: ['2168-2364', '2168-2356']
DOI: https://doi.org/10.1109/mdat.2023.3275049